Paper 3.2 Abstraction of RTL IPs into Embedded Software

ABSTRACT
1. INTRODUCTION
2. SW CODE GENERATION ALGORITHM
2.1 EFSM generation
2.2 Merge of processes
2.3 Abstraction of HDL scheduler
It is like sitting the presentation of other team's work.
2.4 Definition of interface and communication protocol
3. EXPERIMENTAL RESULTS
4. CONCLUSIONS

Paper 3.1 A Mixed-Mode Vector-Based Dataflow Approach for Modeling and Simulating LTE Physical Layer

ABSTRACT
Long Term Evolution (LTE)
synchronous dataflow (SDF)
Mixed mode Vector-based Dataflow (MVDF)

1. INTRODUCTION
In SDF, a system is represented as a dataflow graph consisting of functional models.

The effort in using SDF/TSDF to develop physical layer reference designs, however, encounters fundamental limitations due to the constant rate constraint in SDF semantics.

2. BACKGROUND
3. RELATED WORK
4. LTE PHYSICAL LAYER ANALYSIS
In this section, we analyze LTE physical layer from dataflow point of view.

A transport block, denoted as a = a0, a1, . . . , aA−1, where A is the transport block size, is a sequence of bits to be transmitted in the shared channel to a user or a set of users.

5. MIXED-MODE VECTOR-BASED DATAFLOW
6. SIMULATION RESULTS

2.1 Post-silicon Validation Challenges: How EDA and Academia Can Help

1. INTRODUCTION
Post-Silicon validation of large microprocessor designs entails testing of components in a system setting.

It involves multiple different aspects, such as logic validation and debug, electrical validation and debug, and debugging software and customer issues.

The disciplines of post-silicon validation include System Validation (SV), Compatibility Validation (CV), and Electrical Validation (EV)

2. CHALLENGES OF POST-SILICON VALIDATION
In addition, JTAG ports, used to control many of the DFV hooks on the die, are too slow for real-time control and synchronization of events.
(calling for new ways of controlling DFV hooks)

3. SOLUTION VECTORS
3.1 Pre-silicon Engagement
3.2 Post-silicon Opportunities
3.3 Survivability (Post-silicon Debug and Infield Repair)
To assist with debug of the issues in the post-silicon phase and to survive issues in the field, designs need to implement comprehensive survivability features.

3.4 EDA and Research Opportunities

1 EDA Challenges and Options: Investing for the Future

"Overall, it is likely that a set of design cost driven challenges such as design productivity, power management, design for manufacturability, signal integrity, and reliability, will continue to dominate the EDA roadmaps."

Silicon technology complexity
driven challenges can be generally classified as:
--Leakage, power management, circuit/device
innovation, current delivery;
--Signal integrity analysis and management,
--Manufacturing variability
--Manufacturing handoff, NRE cost
--Scaling of global interconnect performance
relative to device performance.
--Decreased reliability ,electro-migration, SER,
fault-tolerance.

Challenges driven by system complexity [1] can be generally classified as:
--Reuse, hierarchical design, heterogeneous SOC
integration especially for mixed-signal
--Verification and test
--Cost-driven design optimization, co-optimization
at die-package-system levels
--Embedded software design, co-design with
hardware and for networked system
environments
-- Reliable implementation platforms, chip
implementation onto multiple circuit fabrics,
higher-level handoff to implementation
-- Design process management—design team size
and geographic distribution, data management,
collaborative design support.